Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - SDRAM FPGA

Search list

[MPI] sdram_verilog_lattice

Description: 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度就可以了.-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of it.
Platform: | Size: 187392 | Author: chen qiming | Hits:

[Other Embeded program] flash_erase

Description: FPGA flash 编程序,使用CYCLONE和FLASH-FPGA flash-programmed, the use of CYCLONE and FLASH
Platform: | Size: 318464 | Author: chunlin_lai | Hits:

[Software Engineering] sdrsdramuse

Description: 一篇讲解ALTERA的FPGA如何实现SDR SRAM的指导文章。很有指导意义。-ALTERA s FPGA on a how to achieve the guidance of SDR SRAM articles. Great guiding significance.
Platform: | Size: 701440 | Author: kurt | Hits:

[VHDL-FPGA-Verilog] H1wQqGvI

Description: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
Platform: | Size: 777216 | Author: 黄辉辉 | Hits:

[Graph program] VGA

Description: 利用fpga控制VGA显示，很实用的，对于初学FPGA的同志，有帮助。-FPGA to control the use of VGA display, it is useful for the beginner FPGA comrades, helpful.
Platform: | Size: 438272 | Author: 杜菲 | Hits:

[Software Engineering] Cyclone2_PCB_and_SCH

Description: 1，原创 cyclone 2开发板，希望能对FPGA电子爱好者有一点设计帮助。 2，本PCB可以与开发者自己的PCB实现扩展。 3，注意接口已经提供5v,-5v，+3.3v,+1.2v输出。 4，带一个LED显示器，多路拨动开关，一个复位健。 5，晶振源兼容5种封装，其中一种是支持9v、5W高精度恒温晶振。 6，fpga内部2个PLL相互连接可以实现0－200MHz内任意频率输出。
Platform: | Size: 529408 | Author: M | Hits:

[SCM] source_code

Description: 一些源程序，主要包括CAN总线驱动、sdram VHDL实现、ucos2的移植、SDIO驱动、tcpip的实现、usb控制器代码、基于FPGA的雷达目标模拟器等-Some source code, including CAN bus driver, sdram VHDL implementation, ucos2 transplant, SDIO drivers, tcpip of implementation, usb controller code, based on the FPGA, such as radar target simulator
Platform: | Size: 6898688 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] sdram_vhd

Description: FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
Platform: | Size: 2186240 | Author: yuhl | Hits:

[VHDL-FPGA-Verilog] sdramled

Description: alter FPGA，包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0，system involved an sdram
Platform: | Size: 1414144 | Author: 吴波 | Hits:

[VHDL-FPGA-Verilog] VerilogfoFPGAbasedSDRAMController

Description: 使用Verilog实现基于FPGA的SDRAM控制器-The use of Verilog for FPGA-based SDRAM Controller
Platform: | Size: 1680384 | Author: he | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl1

Description: FPGA读写SDRAM的VHDL程序，已经测试过-FPGA to read and write the VHDL procedures SDRAM have been tested
Platform: | Size: 5120 | Author: 钟灿武 | Hits:

[VHDL-FPGA-Verilog] SDRAM_VerilogCode

Description: 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
Platform: | Size: 26624 | Author: 姜琰俊 | Hits:

[VHDL-FPGA-Verilog] FPGA_SDRAM_PCI

Description: 一个基于FPGA的PCI数据采集程序，包括SDRAM控制，PCI9054时序控制，开发语言verilog，开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
Platform: | Size: 2798592 | Author: 李国扬 | Hits:

[VHDL-FPGA-Verilog] cameralink

Description: 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Platform: | Size: 13312 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[VHDL-FPGA-Verilog] my_sram

Description: 在sopc builder 中填加SDRAM(IS61LV25616AL),能够直接被系统识别。-Sopc builder filled in Canada in the SDRAM (IS61LV25616AL), the system can be directly identified.
Platform: | Size: 20480 | Author: desd | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Platform: | Size: 488448 | Author: peace | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] lcd2vga_um

Description: LCD加速芯片，用fpga+sdram做的-LCD acceleration chip, using fpga+ sdram do
Platform: | Size: 980992 | Author: 李锦龙 | Hits:
« 1 2 3 4 56 7 8 9 10 ... 15 »

CodeBus www.codebus.net